Design and formal verification of security mechanisms against fault-injection attacks CentraleSupélec in France

A PhD position is available at CentraleSupélec in Rennes, France, as part of the TwinSec national research project, focusing on hardware/software security. The research will address the design and formal verification of security mechanisms to protect against fault-injection attacks, with key areas including formal verification, hardware/software contracts, countermeasures for fault injection, and microarchitecture security.

The project is supervised by Guillaume Hiet (CentraleSupélec), Damien Couroussé (CEA), and Mathieu Jan (CEA), and is affiliated with the SUSHI research team and IRISA Lab. Applicants should have skills in hardware design (Verilog/VHDL) or formal methods (Coq, SMT solvers), and an interest in hardware security and fault attacks.

Prior experience is a plus but not required. The start date is before the end of 2025, and there is an option for a Master's internship before the PhD. For more information and application instructions, see the provided link or contact the supervisors directly.