PhD in AI-assisted Generation of Functional and Formal Hardware Models for EDA and RISC-V CEA in France

CEA-List is recruiting a PhD candidate for a thesis in AI-assisted generation of functional and formal hardware models, with a strong focus on Large Language Models (LLMs), Electronic Design Automation (EDA), and RISC-V architectures.

The project is hosted at CEA in Saclay, France, within the Laboratoire Environnement de Conception et Architecture (LECA) of the Institut LIST. The research sits at the intersection of computer architecture, embedded systems, hardware modeling, and formal verification. The goal is to develop an AI-driven methodology for co-generating executable functional models and formal verification models directly from design specifications, reducing manual effort and improving correctness and consistency.

The thesis will explore generation pipelines based on LLMs, reinforcement learning, and tool-driven feedback loops to iteratively refine intermediate representations and improve model quality. The work will be evaluated on realistic and open-source hardware case studies, especially RISC-V processors, extensions, and accelerators.

Eligibility highlights: a Master’s degree in computer architecture, computer engineering, embedded systems, or computer science; strong skills in Python and C/C++; interest in hardware architecture, EDA, or verification; and a good foundation in machine learning. Familiarity with formal methods is a plus.

Funding / duration: doctoral thesis position for 36 months, starting September 2026. The post does not specify stipend or tuition details in the provided text.

How to apply: consult the official CEA vacancy and the INSTN thesis page, then follow the application instructions on the posting. The announcement links to the official job page and thesis page for further details.