Bernhard Stampfer

TU Wien

Austria

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Articles (12)

Extraction of Charge Trapping Kinetics of Defects From Single-Defect Measurements

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Year:

2024

Revealing the Impact of Gate Area Scaling on Charge Trapping Employing SiO2Transistors

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Year:

2023

Accurate Extraction of Minority Carrier Lifetimes—Part I: Transient Methods

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Year:

2023

Accurate Extraction of Minority Carrier Lifetimes—Part II: Combined I–V C–V Methods

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Year:

2023

Observation of Rich Defect Dynamics in Monolayer MoS2

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Year:

2023

Impact of Bias Temperature Instabilities on the Performance of Power Electronics Employing SiC MOSFETs

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Year:

2023

Oxide and Interface Defect Analysis of lateral 4H-SiC MOSFETs through CV Characterization and TCAD Simulations

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Year:

2023

Physical Modelling of Charge Trapping Effects in SiC MOSFETs

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Year:

2023

Single- Versus Multi-Step Trap Assisted Tunneling Currents—Part I: Theory

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Year:

2022

Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

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Year:

2022

Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies

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Year:

2021

Toward Automated Defect Extraction From Bias Temperature Instability Measurements

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Year:

2021

Collaborators (2)

Tibor Grasser

Professor

TU Wien

AUSTRIA

Theresia Knobloch

TU Wien

AUSTRIA

Bernhard Stampfer

Research Interests

Explore related searches

Contact this professor

Articles (12)

Extraction of Charge Trapping Kinetics of Defects From Single-Defect Measurements

Revealing the Impact of Gate Area Scaling on Charge Trapping Employing SiO2Transistors

Accurate Extraction of Minority Carrier Lifetimes—Part I: Transient Methods

Accurate Extraction of Minority Carrier Lifetimes—Part II: Combined I–V C–V Methods

Observation of Rich Defect Dynamics in Monolayer MoS2

Impact of Bias Temperature Instabilities on the Performance of Power Electronics Employing SiC MOSFETs

Oxide and Interface Defect Analysis of lateral 4H-SiC MOSFETs through CV Characterization and TCAD Simulations

Physical Modelling of Charge Trapping Effects in SiC MOSFETs

Single- Versus Multi-Step Trap Assisted Tunneling Currents—Part I: Theory

Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies

Toward Automated Defect Extraction From Bias Temperature Instability Measurements

Collaborators (2)

Tibor Grasser

Theresia Knobloch

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