Hussam Amrouch

Professor and Head of the Chair of AI Processor Design

Technical University of Munich

Germany

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Hussam Amrouch is a Professor and Head of the Chair of AI Processor Design at the Technical University of Munich in Germany. His research focuses on advanced topics in AI processor design, including transistor modeling, cache modeling, and efficiency in analog synapses. Recent publications include work on cryogenic computing and techniques for secure in-memory AI inference. He contributes significantly to the fields of machine learning vulnerabilities and hardware reliability in next-generation semiconductor technologies.

Hussam Amrouch

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Articles (30)

Kolmogorov–Arnold Network for Transistor Compact Modeling

Cryo-CACTI: Cryogenic-Aware CACTI for Cache Modeling Down to 10K in Advanced 7nm FinFETs

Capacitor Minimization in Analog Synapses for Efficient and Compact Binarized SNNs

Dual Neural Network Framework with SPICE Integration for Fast and Accurate Transistor Modeling

On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning

A Lightweight PUF-Based Weights Obfuscation Technique for Secure In-Memory AI Inference

An Investigation of Minimum Supply Voltage of 5-nm SRAM From 300 K Down to 10 K

CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability

Cryogenic Hyperdimensional In-Memory Computing Using Ferroelectric TCAM

Domain-Specific Hyperdimensional RISC-V Processor for Edge-AI Training

Thermal Effects on Monolithic 3D Ferroelectric Transistors for Deep Neural Networks Performance

A Physics-Based Model for Oxide–Semiconductor-Based Ferroelectric Field-Effect Transistors

Approximation- and Quantization-Aware Training for Graph Neural Networks

Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware

Comprehensive Modeling of Switching Behavior in BEOL FeFET for Monolithic 3-D Integration

FeFET Reliability Modeling for In-Memory Computing: Challenges, Perspective, and Emerging Trends

ML-TCAD: Accelerating FeFET Reliability Analysis Using Machine Learning

Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability

In-Memory Acceleration of Hyperdimensional Genome Matching on Unreliable Emerging Technologies

WaSSaBi: Wafer Selection With Self-Supervised Representations and Brain-Inspired Active Learning

Golden-Free Robust Age Estimation to Triage Recycled ICs

HW/SW Co-Design for Reliable TCAM- Based In-Memory Brain-Inspired Hyperdimensional Computing

Massively Parallel Circuit Setup in GPU-SPICE

Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing

Machine Learning-Based Microarchitecture- Level Power Modeling of CPUs

Brain-Inspired Hyperdimensional Computing: How Thermal-Friendly for Edge Computing?

Compact CMOS-Compatible Majority Gate Using Body Biasing in FDSOI Technology

HW/SW Codesign for Approximation-Aware Binary Neural Networks

Targeting DNN Inference Via Efficient Utilization of Heterogeneous Precision DNN Accelerators

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Collaborators (8)

Xiaobo Hu

Jinjun Xiong

Iraklis Anagnostopoulos

Andreas Gerstlauer

Ozgur Sinanoglu

Jian-Jia Chen

Paulo Flores

Fanny Spagnolo

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