Robert Staszewski

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Full Professor

Dublin City University

Ireland

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Robert Staszewski is a Full Professor at University College Dublin in Ireland. His research areas include digital-to-time converters, analog-to-digital converters, phase-locked loops, and advanced techniques for RF and mm-Wave frequency synthesis. He has authored several articles addressing low-noise circuit design and innovative strategies for frequency calibration and spurious cancellation.

Recent Grants

Grant: Open

Mixed-Signal Integrated Circuits Electronics for Emerging Applications

Open Date: 2022-12-01

Close Date: 2028-12-01

Grant: Open

CONNECT_Phase 2

Open Date: 2021-01-01

Close Date: 2026-12-01

Grant: Close

Mixed-Signal Integrated Circuit Electronics to Enable the Internet-of-Things

Open Date: 2014-10-01

Close Date: 2019-10-01

Grant: Close

Time-Domain Analog and RF Signal Processing

Open Date: 2012-09-01

Close Date: 2017-09-01

Robert Staszewski

Research Interests

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About

Recent Grants

Articles (24)

A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique

A Low-Noise Digital-to-Time Converter Exploiting Waveform of Integrated Crystal Oscillator

A 7-bit 1.41-GS/s 2-bit/Cycle Precharge-Advancing SAR ADC With Fast Discharge Comparator

A Charge-Domain Fractional-N ADPLL Based on Charge-Steering Sampling

A PLL Technique: Charge-Steering Sampling

A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations

Analysis of Fractional Spurs in a DTC-Assisted ADPLL Exploiting Crystal-Oscillator Waveform With Harmonic-Based Digital Predistortion

Beyond ADPLLs for RF and mm-Wave Frequency Synthesis: Watching out for new techniques: oversampling-reference and charge-sharing locking

Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop

Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop

Nanoscale single-electron box with a floating lead for quantum sensing: modelling and device characterization

Nanoscale single-electron box with a floating lead for quantum sensing: Modeling and device characterization

RFIC Reuse Techniques to Enable Ultra-Low-Power IoT: A Tutorial

8-Shaped Inductors: An Essential Addition to RFIC Designers’ Toolbox

A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

Exploring Speed Maximization of Frequency-to-Digital Conversion for Ultra-Low-Voltage VCO-Based ADCs

An Edge-Combining Frequency-Multiplying Class-D Power Amplifier

A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion

A Gm -Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing

A Charge-Sharing IIR Filter With Linear Interpolation and High Stopband Rejection

Design of High-IF Discrete-Time Receivers for IoT: Demystifying Aliasing Trade-Offs

Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

Collaborators (6)

Andrew Mitchell

Panagiotis Giounanlis

KAI XU

Anding Zhu

Teerachot Siriburanon

Elena Blokhina

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