Serge Ecoffey

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Université de Sherbrooke
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Canada

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Professor Serge Ecoffey is a faculty member at Université de Sherbrooke in Canada. His research focuses on advanced materials and semiconductor technologies, with recent publications including work on CMOS-compatible ferroelectric memory, hydrogen sensors, and memristors. He also explores innovative techniques for nano-patterning and etching processes, contributing substantially to the field of microelectronics.

Positions (1)

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Université de Sherbrooke

Université de Sherbrooke

PhD and Postdoctoral Opportunities in Advanced Microelectronic Packaging, FOWLP, and Thermal Management at Université de Sherbrooke

Université de Sherbrooke and IBM are advertising three postdoctoral opportunities and related PhD-level research projects in advanced microelectronic packaging , with a strong focus on Fan-Out Wafer-Level Packaging (FOWLP) , heterogeneous integration , microfabrication , and thermal management . The projects are hosted in the INPAQT ecosystem and carried out mainly at the Interdisciplinary Institute for Technological Innovation (3IT) and the MiQro Innovation Collaborative Center (C2MI) in Bromont, Canada, in collaboration with IBM Canada . The research environment is described as highly applied, with state-of-the-art infrastructure and direct industrial collaboration. Postdoc 1 focuses on an integrated vapor chamber cooling system for high-density FOWLP. The work includes thermal resistance modeling, thermomechanical and fluidic simulation, vapor chamber fabrication using microfabrication techniques such as Si etching and gold-gold bonding, thermal characterization, and integration into an advanced packaging test vehicle. Postdoc 2 focuses on optimization of microfabrication processes for micropillars in FOWLP. The project targets ultra-fine pitch Cu/Ag/Sn micropillars, lithography and alignment, electroplating optimization, thermocompression bonding conditions, and morphological characterization for high-density vertical interconnections. Postdoc 3 focuses on temporary bonding and debonding processes for FOWLP. The successful candidate will develop temporary carrier and release-tape processes, study material properties and process conditions, and validate integrity after chip interconnection in close collaboration with IBM engineers. The PhD-related project pages also indicate research opportunities in mechanical engineering and electrical engineering , with funding offered at $25,000 CAD per year . The postdoctoral project lists $50,000 annually . The work is part of an IBM/NSERC Alliance Project on multi-chip heterogeneous integration for high-performance computing. Eligibility highlights include a master’s degree for the PhD projects or a PhD for the postdoc, plus experience or strong interest in clean-room work, microfabrication, thermal modeling, packaging, and experimental characterization. English or French communication skills are required. Application materials mentioned include a cover letter, CV, transcripts, and references or recommendation letters depending on the project. Application timing in the post points to a September 2025 start date, and the linked project pages were updated in late 2025 and March 2026. Interested candidates should use the Université de Sherbrooke project portal and the contact emails provided to express interest and submit the requested documents.

11 months ago

Articles (14)

Analog programming of CMOS-compatible Al2O3/TiO2−x memristor at 4.2 K after metal-insulator transition suppression by cryogenic reforming

Exploration of memristors' behavior at cryogenic temperatures has become crucial due to the growing interest in quantum computing and cryogenic electronics. In this context, our study focuses on the characterization at cryogenic temperatures (4.2 K) of TiO2−x-based memristors fabricated with a CMOS-compatible etch-back process. We demonstrate a so-called cryogenic reforming (CR) technique performed at 4.2 K to overcome the well-known metal-insulator transition (MIT), which limits the analog behavior of memristors at low temperatures. This cryogenic reforming process was found to be reproducible and led to a durable suppression of the MIT. This process allowed to reduce by ∼20% the voltages required to perform DC resistive switching at 4.2 K. Additionally, conduction mechanism studies of memristors before and after cryogenic reforming from 4.2 to 300 K revealed different behaviors above 100 K, indicating a potential change in the conductive filament stoichiometry. The reformed devices exhibit a conductance level that is 50 times higher than ambient-formed memristor, and the conduction drop between 300 and 4.2 K is 100 times smaller, indicating the effectiveness of the reforming process. More importantly, CR enables analog programming at 4.2 K with typical read voltages allowing to store up to 4 bits of information on a single CR memristor. Suppressing the MIT improved the analog switching dynamics of the memristor leading to ∼250% larger on/off ratios during long-term depression (LTD)/long-term potentiation (LTP) resistance tuning. This enhancement opens up the possibility of using TiO2−x-based memristors to be used as synapses in neuromorphic computing at cryogenic temperatures.

Year:

2023

Collaborators (8)

Dominique Drouin

-

CANADA

Andreas Ruediger

Full professor (since 2016)

Institut national de la recherche scientifique

CANADA

Paul Charette

Professor

Université de Sherbrooke

CANADA

Serge Charlebois

Professor

Université de Sherbrooke

CANADA

Fabien Alibart

Institut d'Électronique de Microélectronique et de Nanotechnologie

FRANCE

Tejinder Singh

Chief Architect and Engineering Research Lead (2024-Present), Senior Principal Member of Technical Staff (2023-2024), Principal Member of Technical Staff (2021-2023)

-

CANADA

Denis Machon

CNRS

CANADA

Amirali Amirsoleimani

Assistant Professor

York University

CANADA
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