Andrés Otero

Assistant Professor

Universidad Politécnica de Madrid

Spain

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Andrés Otero is an Assistant Professor at Universidad Politécnica de Madrid, Spain. His research focuses on incremental machine learning applications, reconfigurable systems modeling, and smart edge computing, with recent articles exploring dynamic workloads and fault diagnosis in industrial IoT. He also investigates deep learning techniques for fear recognition and hyperspectral image compression within adaptive computing platforms.

Articles (12)

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2025

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2024

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2024

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2023

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2022

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2021

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2021

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2021

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2020

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2020

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2020

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2020

Collaborators (7)

Jose Nunez-Yanez

University of Bristol

UNITED KINGDOM

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José M. Lanza-Gutiérrez

Universidad de Alcalá

SPAIN

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Jorge Portilla

Associate Professor

Universidad Politécnica de Madrid

SPAIN

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Marco Platzner

University of Paderborn

GERMANY

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MIGUEL HOLGADO BOLAÑOS

Universidad Politécnica de Madrid

SPAIN

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Roberto Sarmiento

Full Professor

Universidad de Las Palmas de Gran Canaria

SPAIN

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Junjiao Sun

Universidad Politécnica de Madrid

SPAIN

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Andrés Otero

Research Interests

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Articles (12)

Leveraging Incremental Machine Learning for Reconfigurable Systems Modeling under Dynamic Workloads

A Deep Learning Approach for Fear Recognition on the Edge Based on Two-Dimensional Feature Maps

Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloads

Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs

A Machine Learning-Based Methodology for in-Process Fluid Characterization With Photonic Sensors

Multi-grain reconfigurable and scalable overlays for hardware accelerator composition

A Machine-Learning-Based Distributed System for Fault Diagnosis With Scalable Detection Quality in Industrial IoT

Lossy Hyperspectral Image Compression on a Reconfigurable and Fault-Tolerant FPGA-Based Adaptive Computing Platform

A Dynamically Reconfigurable BbNN Architecture for Scalable Neuroevolution in Hardware

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation

Collaborators (7)

Jose Nunez-Yanez

José M. Lanza-Gutiérrez

Jorge Portilla

Marco Platzner

MIGUEL HOLGADO BOLAÑOS

Roberto Sarmiento

Junjiao Sun

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