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CHIRN CHYE BOON

Assocociate Professor

Nanyang Technological University (NTU)

Singapore

Research Interests

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About

Chirn Chye Boon is an Associate Professor at Nanyang Technological University, Singapore. His research areas include phase-locked loops (PLLs), low-noise amplifiers, and time-domain analog-to-digital converters, as reflected in his recent publications. He has contributed to advancements in CMOS technology for high-frequency applications, focusing on enhancing noise performance and reducing reference spurs in PLL designs.

Articles (14)

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2026

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2026

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2024

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2024

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2023

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2022

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2022

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2022

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2022

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2022

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2022

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2022

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2021

Collaborators (5)

Qian Chen

Nanyang Technological University (NTU)

SINGAPORE

View details

Liter Siek

Nanyang Technological University (NTU)

SINGAPORE

View details

Herman Ng

Professor

Hochschule Karlsruhe Technik und Wirtschaft

GERMANY

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Zhongyuan Fang

Full Professor

Southeast University

CHINA

View details

Yuan Liang

Nanyang Technological University (NTU)

SINGAPORE

View details

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CHIRN CHYE BOON

Research Interests

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About

Articles (14)

An 88.2-to-102.5-GHz Phase-Locked Signal Source Featuring −77.8-dBc Reference Spur and 67.6-fsrms Integrated Jitter in 28-Nm CMOS Technology

A 33.2–43.2-GHz 2.17-dB NF LNA Exploiting Tri-Coil Transformer-Based Gm -Boosting and Noise Suppression Technique

A 28.8-to-43.2 GHz 79.8 fsrms Jitter and −78.5 dBc Reference Spur PLL Exploiting Complementary Mixing Phase Detector With Mismatch Calibration

A 0.6 V, 1.74 mW, 2.9 dB NF Inductorless Wideband LNA in 28-nm CMOS Exploiting Noise Cancellation and Current Reuse

A Single-Channel Voltage-Scalable 8-GS/s 8-b >37.5-dB SNDR Time-Domain ADC With Asynchronous Pipeline Successive Approximation in 28-nm CMOS

A Dual-Path Subsampling PLL With Ring VCO Phase Noise Suppression

A 0.092-mm2 2–12-GHz Noise-Cancelling Low-Noise Amplifier With Gain Improvement and Noise Reduction

An Equivalent-Time Sampling Millimeter-Wave Ultra-Wideband Radar Pulse Digitizer in CMOS

A 23.4 mW −72-dBc Reference Spur 40 GHz CMOS PLL Featuring a Spur-Compensation Phase Detector

A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique

A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fsrms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

A 13.5-Gb/s 140-GHz Silicon Redriver Exploiting Metadevices for Short-Range OOK Communications

A 0.6 V 4 GS/s −56.4 dB THD Voltage-to-Time Converter in 28 nm CMOS

A Bidirectional Nonlinearly Coupled QVCO With Passive Phase Interpolation for Multiphase Signals Generation

Collaborators (5)

Qian Chen

Liter Siek

Herman Ng

Zhongyuan Fang

Yuan Liang

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