Daniele Rossi

Associate Professor

University of Pisa

Italy

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About

Daniele Rossi is an Associate Professor at the University of Pisa, Italy. His research interests include cybersecurity, automotive networking systems, machine learning applications in hardware design, and analog circuit reliability in harsh environments. Recent publications focus on cybersecurity in automotive networks, advanced voltage sampling techniques, and aging resilient circuits for secure applications.

Articles (19)

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2025

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2020

Collaborators (1)

Sergio Saponara

University of Pisa

ITALY

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Daniele Rossi

Research Interests

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About

Articles (19)

Cybersecurity of Automotive Wired Networking Systems: Evolution, Challenges, and Countermeasures

CANini: In-Depth Traffic Analysis for Design and Robustness Evaluation of DTree-Based IDS in Automotive Networking Systems

Modeling, Analysis, and Comparison of Voltage and Charge Sampling Techniques in Sub-Sampling PLL Design

On-Chip Age Estimation Using Machine Learning

HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS Improvement

Radiation Hardened Domino Logic-Based Schmitt Trigger Circuit With Improved Noise Immunity

Aging resilient ring oscillators for reliable Physically Unclonable Functions (PUFs)

An Integrated Charge Pump for Phase-Locked Loop Applications in Harsh Environments

Design and Experimental Verification of a 6.25-GHz PLL for Harsh Temperature Conditions in 65-nm CMOS Technology

Design of Linear and Planar Arrays With Low Sidelobe Levels and High Directivity Using Two-Way Array Factor

Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology

A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications

Hardware Trojan Detection on a PCB Through Differential Power Monitoring

Online Remaining Useful Lifetime Prediction Using Support Vector Regression

Run-Time Thermal Management for Lifetime Optimization in Low-Power Designs

Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs

Run-Time Protection of Multi-Core Processors From Power-Noise Denial-of-Service Attacks

Run-Time Protection of Multi-Core Processors from Power-Noise Denial-of-Service Attacks

Soft error hardening enhancement analysis of NBTI tolerant Schmitt trigger circuit

Collaborators (1)

Sergio Saponara

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