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Hao Yu

Professor

Nanyang Technological University

Singapore

Research Interests

About

Hao Yu is an Assistant Professor at Nanyang Technological University in Singapore. His research areas include event camera classification, microfluidic bio-imaging, and the development of highly efficient computing accelerators for deep learning and edge applications. He has recently published articles exploring innovative solutions in hardware optimization and electromagnetic interference shielding.

Articles (18)

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2026

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2025

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2024

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2024

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2023

Collaborators (2)

Ruilin Zhang

Program-specified Assistant Professor

Kyoto University

JAPAN

View details

Longyang Lin

Assistant Professor

Southern University of Science and Technology (SUSTech)

CHINA

View details

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Hao Yu

Research Interests

About

Articles (18)

A 22-nm End-to-End Edge--AI Processor With Booth-Value-Confined Acceleration and Hardware-Aware Layer-Wise Model Deployment

Frieren: A Fault-Tolerant Reconfigurable Energy-Efficient Computing Architecture With Enhanced Reliability in Harsh Environments

A Neural Architecture Search Optimized Mixed-Precision Systolic-in-Systolic DNN Accelerator on FPGA

A UHD@60fps Perceptual Texture-Aware Local Dimming Processor for Mini-LED HDR Displays

APTQ+: Attention-FFN-aware Post-Training Quantization for a Layer-wise LLM Accelerator on FPGA

EdgeLUT: Ultra-Efficient Configurable LUT-Based Edge Accelerator for Fixed-Resolution Image Restoration

Rethinking Efficient and Effective Point-Based Networks for Event Camera Classification and Regression

Artificial Intelligence-Assisted Microfluidic Bio-Imaging—From Sensors to Applications: A Review

A 29.12-TOPS/W Vector Systolic Accelerator With NAS-Optimized DNNs in 28-nm CMOS

EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models

A Layer-wised Mixed-Precision CIM Accelerator with Bit-level Sparsity-aware ADCs for NAS-Optimized CNNs

Fast Routing Algorithm for Mask Stitching Region of Ultra Large Wafer Scale Integration

A Reconfigurable Processing Element for Multiple-Precision Floating/Fixed-Point HPC

A 28-nm 135.19 TOPS/W Bootstrapped-SRAM Compute-in-Memory Accelerator with Layer-Wise Precision and Sparsity

A Generalized Microwave Absorption Criterion of Two-Port Networks for Electromagnetic Interference Shielding

A Low-Power Charge-Domain Bit-Scalable Readout System for Fully-Parallel Computing-in-Memory Accelerators

A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier

An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge

Collaborators (2)

Ruilin Zhang

Longyang Lin

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