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Hyun Kim

Associate Professor

Seoul National University

South Korea

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About

Dr. Hyun Kim is an Associate Professor at Seoul National University of Science and Technology, South Korea. His research areas include lightweight convolutional neural networks, object detection using spiking neural networks, and efficient hardware architecture for deep learning applications. Recent publications reflect his focus on advanced algorithms and frameworks, as well as performance optimization in computer architecture.

Articles (23)

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Collaborators (4)

Mingoo Seok

Columbia University

UNITED STATES

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Sunwoong Kim

Assistant Professor

Rochester Institute of Technology

UNITED STATES

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Min-Seong Choo

Assistant Professor

Yonsei University

SOUTH KOREA

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Seokbum Ko

Department Head and Professor

University of Saskatchewan

CANADA

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Hyun Kim

Research Interests

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About

Articles (23)

SLAKE: Softmax-approximated training-free linear attention with KV-Cache eviction for long-sequence LLMs

FLASH: Energy-Efficient FPGA Acceleration via Linear Approximation and Streamlined Two-Stage Pipeline Architectures for Quantized CNN--Transformer Hybrid Networks

SPEED: Structured kernel block pruning with filter groups for efficient and elastic SW-HW co-design in FPGA-based CNN accelerators

KWS-CIM: A Charge-Domain eDRAM-Based Compute-in-Memory Macro for Ternary DFSMN Keyword Spotting

GQ-Train: Gradient Quantization-aware CNN Training with adaptive thresholding and hardware-friendly stochastic rounding unit

HERMeS: H igh-Fidelity and High-Speed E mulation with a R econfigurable Framework for DRAM-Based Processing-in- M emory S ystems

Towards efficient language giants: A comprehensive survey on structural optimizations and compression techniques for large language models

Accelerating language giants: A survey of optimization strategies for LLM inference on hardware platforms

BGM: A Block Processing Unit-Integrated GEMM Accelerator for Hardware-Efficient LLM Inference via Outlier-Aware Merge-and-Split Block Quantization

S$$^3$$-Prune: Stability-Aware Token Budgeting for Long-Form Video-Language Models

SHARP: Shift-Aware Hybrid Power-of-Two Quantization-Assisted Real-Time Vision Transformer Inference on FPGA Platforms

VFT: A versatile fine-tuning scheme based on feature distribution-aware knowledge distillation for lightweight convolutional neural networks

VFF-Net: Evolving forward–forward algorithms into convolutional neural networks for enhanced computational insights

BN-SNN: Spiking neural networks with bistable neurons for object detection

Attention-Based Deep Feature Aggregation Network for Skin Lesion Classification

NPC: A Non-Conflicting Processing-in-Memory Controller in DDR Memory Systems

Lightweight Deepfake Detection Based on Multi-Feature Fusion

MCM-SR: Multiple Constant Multiplication-Based CNN Streaming Hardware Architecture for Super-Resolution

Survey of CPU and memory simulators in computer architecture: A comprehensive analysis including compiler integration and emerging technology applications

FAB: FPGA-Accelerated Fully-Pipelined Bottleneck Architecture With Batching for High-Performance MobileNetv2 Inference

Evaluation of 2T0C DRAM-Based Processing-in-Memory Systems for Accelerating Deep Neural Network Models

USD: Uncertainty-Based One-Phase Learning to Enhance Pseudo-Label Reliability for Semi-Supervised Object Detection

Mobile-X: Dedicated FPGA Implementation of the MobileNet Accelerator Optimizing Depthwise Separable Convolution

Collaborators (4)

Mingoo Seok

Sunwoong Kim

Min-Seong Choo

Seokbum Ko

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