Jaan Raik

TalTech’s Centre for Dependable Computing Systems, within the Department of Computer Systems at Tallinn University of Technology, is seeking a Postdoctoral Researcher in hardware design with a focus on RISC-V architectures, custom hardware, and AI accelerators . The position is embedded in two nationally funded research projects. The first, SPARK-CHIP , develops scalable, parametrizable hardware kernels for cost-effective AI accelerator chips, taking ideas from architecture exploration through RTL implementation to silicon validation. The second, RISC-V for Fault-Tolerant Quantum Computing , is a joint project with the University of Tartu focused on RISC-V-based many-core hardware and ISA extensions for classical control and error-correction tasks in fault-tolerant quantum computing. The successful candidate will lead hardware architecture and design across both projects, including specification, RTL, verification, and tape-out. Responsibilities also include designing custom RISC-V ISA extensions and the associated hardware-software co-design flow, developing and optimizing AI accelerator architectures and hardware kernels, guiding PhD students, coordinating technical work, and contributing to publications, project delivery, and future proposals. This is a full-time, 2-year postdoctoral contract with a possibility of extension. The position offers a competitive salary of 3,000–3,300 EUR/month , access to chip design tools, FPGA platforms, and tape-out opportunities, and close collaboration with PhD students as well as national and international partners. The research environment is described as one of Europe’s leading groups in dependable computing. Applicants must hold a PhD in computer engineering, electrical engineering, or a closely related field, with specialization in hardware design. Essential experience includes RISC-V and ISA extensions, hardware-software co-design, custom hardware design, computer architecture, digital hardware design through tape-out, AI accelerator architectures, independent research, project/team management, and excellent English. Preferred experience includes ASIC flows, FPGA prototyping, hardware dependability/fault tolerance, quantum computing knowledge, and proposal writing. The application deadline is 15 December 2026 . Candidates should apply online and submit a cover letter, a short research statement, PhD diploma, thesis link, full publication list, and references.