Jaewon Jang

Assistant Prof.

Kyungpook National University

South Korea

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About

Jaewon Jang is an Assistant Professor at Kyungpook National University in South Korea. His research areas include nonvolatile memory characteristics, solution-processed thin-film transistors, and materials for resistive random-access memory. Recent articles authored by Professor Jang focus on improving the performance of devices using sol-gel processes and innovative electrode materials.

Articles (14)

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2024

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2024

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2024

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2024

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2023

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2023

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2023

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2023

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2023

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2022

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2022

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2022

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2022

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2022

Collaborators (3)

Jin-Hyuk Bae

Kyungpook National University

SOUTH KOREA

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Sangwoo Lee

Kyungpook National University

SOUTH KOREA

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In-Man Kang

Kyungpook National University

SOUTH KOREA

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Jaewon Jang

Research Interests

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Articles (14)

UV/Ozone-Treated and Sol–Gel-Processed Y<sub>2</sub>O<sub>3</sub> Insulators Prepared Using Gelation-Delaying Precursors

Dependence of Positive Bias Stress Instability on Threshold Voltage and Its Origin in Solution-Processed Aluminum-Doped Indium Oxide Thin-Film Transistors

Effect of Electrochemically Active Top Electrode Materials on Nanoionic Conductive Bridge Y<sub>2</sub>O<sub>3</sub> Random-Access Memory

Improving the Nonvolatile Memory Characteristics of Sol–Gel-Processed Y<sub>2</sub>O<sub>3</sub> RRAM Devices Using Mono-Ethanolamine Additives

Low-Temperature Enhancement-Mode Amorphous Oxide Thin-Film Transistors in Solution Process Using a Low-Pressure Annealing

Sol–Gel-Processed Y<sub>2</sub>O<sub>3</sub> Multilevel Resistive Random-Access Memory Cells for Neural Networks

Sol–Gel-Processed Y<sub>2</sub>O<sub>3</sub>–Al<sub>2</sub>O<sub>3</sub> Mixed Oxide-Based Resistive Random-Access-Memory Devices

Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries

Improvement in Switching Characteristics and Bias Stability of Solution-Processed Zinc–Tin Oxide Thin Film Transistors via Simple Low-Pressure Thermal Annealing Treatment

Improved Tunneling Property of p+Si Nanomembrane/n+GaAs Heterostructures through Ultraviolet/Ozone Interface Treatment

Design of a Capacitorless DRAM Based on Storage Layer Separated Using Separation Oxide and Polycrystalline Silicon

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure

Improved Environment Stability of Y<sub>2</sub>O<sub>3</sub> RRAM Devices with Au Passivated Ag Top Electrodes

Physico-Chemical Origins of Electrical Characteristics and Instabilities in Solution-Processed ZnSnO Thin-Film Transistors

Collaborators (3)

Jin-Hyuk Bae

Sangwoo Lee

In-Man Kang

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