Jose Ignacio Garate

Associated Lecturer

University of the Basque Country
Country flagSpain

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About

Jose Ignacio Garate is an Associated Lecturer at the University of the Basque Country UPV/EHU in Spain. His research areas include embedded systems, medical device design, and power electronics, with recent publications focusing on interrupt latency in multiprocessing systems, IEEE 1588 implementation for RISC-V devices, and methodologies for developing embedded sensor systems. He is actively engaged in exploring low-power solutions and semiconductor applications for IoT devices and has contributed significantly to the understanding of high-frequency oscillation attenuation methods.

Articles (7)

IEEE 1588, also known as the Precision Time Protocol (PTP), is a standard protocol for clock synchronization in distributed systems. While it is not architecture-specific, implementing IEEE 1588 on Reduced Instruction Set Computer-V (RISC-V) low-power embedded devices demands considering the system requirements and available resources. This paper explores various approaches and techniques to achieve accurate time synchronization in such instruments. The analysis covers software and hardware implementations, discussing each method’s challenges, benefits, and trade-offs. By examining the state-of-the-art in this field, this paper provides valuable insights and guidance for researchers and engineers working on time-critical applications in RISC-V-based embedded systems, aiding in selecting the most-suitable stack for their designs.

Year:

2024

Modern multiprocessing embedded applications require, in many cases, two different environments on the same platform: one that meets real-time requirements and another one with a general purpose operating system. Although several technologies can be used, two of the most popular are virtualization based on hypervisors and asymmetric multiprocessing software. However, using these tools introduces latency, which must be measured to verify compliance with real-time requirements. With the aim of facilitating these measurements, this work provides a hardware tool that is more precise and easier to use than other existing software solutions. The paper also studies the interrupt latency generated by different hypervisors and asymmetric multiprocessing frameworks in a Zynq UltraScale+ platform. This research work facilitates the accurate study of the temporal response of multiprocessor embedded systems, which allows for evaluating their suitability for applications with real-time requirements.

Year:

2024

Year:

2023

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2022

Year:

2022

Year:

2020

Year:

2020

Collaborators (8)

Unai Ugalde

University of the Basque Country/Euskal Herriko Unibertsitatea (UPV/EHU)

SPAIN
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Jon Andreu

Accreditated as FULL PROFESSOR

University of the Basque Country/Euskal Herriko Unibertsitatea (UPV/EHU)

SPAIN
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Asier Matallana Fernández

Doctor Assitant Professor

University of the Basque Country

SPAIN
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Leire Muguira

Assistant Professor

UPV/EHU

SPAIN
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Jaime Jiménez

University of the Basque Country

SPAIN
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Armando Astarloa Cuéllar

University of the Basque Country

SPAIN
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Unai Bidarte

University of the Basque Country

SPAIN
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José Luis Martín

University of the Basque Country

SPAIN
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