Rolf Drechsler

University of Bremen

Germany

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Articles (20)

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2025

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2022

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2022

Collaborators (2)

Daniel Große

Johannes Kepler University

AUSTRIA

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Klaus McDonald-Maier

Professor of Embedded and Intelligent Systems

University of Essex

UNITED KINGDOM

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Rolf Drechsler

Research Interests

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Articles (20)

MESSI: Task Mapping and Scheduling Strategy for FPGA-based Heterogeneous Real-Time Systems

FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits

Auto-OPS: A Framework for Automated Optical Probing Simulation on GDS-II

LLM-assisted Bug Identification and Correction for Verilog HDL

qSAT: Design of an Efficient Quantum Satisfiability Solver for Hardware Equivalence Checking

Correct and Verify—CAV: Exploiting Binary Decision Diagrams to Enable Formal Verification of Approximate Adders With Correct Carry Bits

OPTI-Sim: Performing Optical Probing Simulation on Layout Design Files

Automated polynomial formal verification using generalized binary decision diagram patterns

Efficient Evolution of Variable Ordering for Binary Decision Diagram Optimization

Exploration of Design Alternatives for Reducing Idle Time in Shor's Algorithm: A Study on Monolithic and Distributed Quantum Systems

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors

Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT

Impact of sneak paths on in-memory logic design in memristive crossbars

Improving the Designs of Nearest Neighbour Quantum Circuits for 1D and 2D Architectures

IMAGIN: Library of IMPLY and MAGIC NOR-Based Approximate Adders for In-Memory Computing

Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing

Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype

Power-aware test scheduling framework for IEEE 1687 multi-power domain networks using formal techniques

RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal

Collaborators (2)

Daniel Große

Klaus McDonald-Maier

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