Sachin Sapatnekar

University of Minnesota

United States

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Articles (19)

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2025

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2022

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2022

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2022

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2022

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2021

Collaborators (6)

Yang Lv

University of Minnesota

UNITED STATES

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Marc Riedel

Faculty, Professor

University of Minnesota

UNITED STATES

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Jiang Hu

UNITED STATES

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Vidya Chhabria

Assistant Professor

Arizona State University

UNITED STATES

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Zhiang Wang

University of California

UNITED STATES

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Jian-Ping Wang

Professor

University of Minnesota System

UNITED STATES

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Sachin Sapatnekar

Research Interests

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Articles (19)

The Case for Secure Miniservers Beyond the Edge

An Analytical Solution for Transient Electromigration Stress in Multisegment Straight-line Interconnects Based on a Stress-wave Model

Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs

Performance Analysis of CNN Inference/Training with Convolution and Non-Convolution Operations on ASIC Accelerators

Mobile-PBR: A 28-nm Energy-Efficient Rendering Processor for Photorealistic Augmented Reality With Inverse Rendering and Background Clustering

An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators

MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs

Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts

GNN-Based Hierarchical Annotation for Analog Circuits

A Stochastic Computing Scheme of Embedding Random Bit Generation and Processing in Computational Random Access Memory (SC-CRAM)

Performance-driven Wire Sizing for Analog Integrated Circuits

Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs

A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route

CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational RAM

OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis

A 1,968-node coupled ring oscillator circuit for combinatorial optimization problem solving

A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, with Efficient Load Balancing and Graph-Specific Caching

Exploring the Feasibility of Using 3-D XPoint as an In-Memory Computing Accelerator

Collaborators (6)

Yang Lv

Marc Riedel

Jiang Hu

Vidya Chhabria

Zhiang Wang

Jian-Ping Wang

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