Shilpa Mehta

In this article, a novel 1.8-5 GHz downconversion mixer is presented. The mixer is designed and simulated using SiGe 8HP 130 nm CMOS process technology. The proposed mixer is implemented by incorporating a double-balanced configuration, active inductor, and current mirror techniques. For performance optimization of the proposed mixer, different algorithms such as the genetic algorithm (GA), inclined plane system optimization (IPO) algorithm, and particle swarm optimization (PSO) algorithm have been used. Compared to existing works, this design shows an enhanced conversion gain (CG), a third-order input intercept point (IIP3), and return loss ( S 11 ) at the expense of the noise figure (NF). Additionally, the design consumes low power and covers a small chip area compared to other state-of-the-art devices. PSO shows the most promising results when compared to other optimization algorithms’ results. According to the measurement results after PSO optimization, the mixer attains a maximum CG of 25 dB, an IIP3 of 4 dBm, and a NF of 5.2 dB at 5 GHz, while consuming only 15 mW of DC power. The mixer operates at 1.2 V and covers 0.8 mm2 die area.