SUDHAKAR PAMARTI

Professor

University of California, Los Angeles

United States

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Sudhakar Pamarti is a Professor at the University of California Los Angeles, USA. His research areas include digital circuit design, artificial intelligence, and memory technologies, with recent contributions focusing on fractional frequency synthesizers, magneto-electric RAM, and stochastic computing architectures. He is dedicated to advancing low-energy operation and secure AI applications in edge computing.

Articles (16)

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2025

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2025

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2025

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2025

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2025

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2024

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2024

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2024

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2024

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2023

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2023

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2023

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2022

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2022

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2021

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2020

Collaborators (5)

Hoi Lee

Professor

University of Texas at Dallas

UNITED STATES

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Christos Papavassiliou

Senior Lecturer

Imperial College London

UNITED KINGDOM

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S. S. Iyer

University of California

UNITED STATES

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Nader Sehatbakhsh

Assistant Professor

University of California

UNITED STATES

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Puneet Gupta

Professor

University of California, Los Angeles

UNITED STATES

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SUDHAKAR PAMARTI

Research Interests

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Articles (16)

A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation

A 65-nm Digital Stochastic Compute-in-Memory CNN Processor With 8-bit Precision

Secure artificial intelligence at the edge

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”

A 180-nm Voltage-Controlled Magneto-Electric RAM With Sub-1-ns Switching Time

SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras

FPGA Crystal Oscillator Circuit Emulation Based on Wave Digital Filter

Design and Analysis of a Fractional Frequency Synthesizer With $<$90-fs Jitter and $<$ $-$103-dBc Spurious Tones Using Digital Spur Cancellation

Digital Residual Alias Cancellation for Filtering-by-Aliasing Receivers

Low-Energy Shared-Current Write Schemes for Voltage-Controlled Spin-Orbit-Torque Memory

REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration

A Nonvolatile Compute-in-Memory Macro Using Voltage-Controlled MRAM and In Situ Magnetic-to-Digital Converter

A Dual-Channel High-Linearity Filtering-by-Aliasing Receiver Front-End Supporting Carrier Aggregation

A 4.4–75-TOPS/W 14-nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator

Periodically Time-Varying Noise Cancellation for Filtering-by-Aliasing Receiver Front Ends

Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC)

Collaborators (5)

Hoi Lee

Christos Papavassiliou

S. S. Iyer

Nader Sehatbakhsh

Puneet Gupta

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