Tae Hyoung Kim

Assistant Professor

Nanyang Technological University (NTU)

Singapore

Research Interests

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About

Tae Hyoung Kim is an Assistant Professor at Nanyang Technological University, Singapore. His research interests focus on advanced computing architectures, including time-based transceivers, compute-in-memory technologies, and energy-efficient processing for IoT devices. Recent publications include work on linear voltage-to-time converters, energy-efficient self-organizing map processors, and enhancements in image processing techniques.

Articles (29)

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2022

Collaborators (5)

YONGTAE KIM

Assistant Professor

Kyungpook National University

SOUTH KOREA

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Yong Shim

Chung-Ang University

SOUTH KOREA

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Wen Siang Lew

Professor

Nanyang Technological University (NTU)

SINGAPORE

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Bongjin Kim

UNITED STATES

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Pieter Harpe

Associate Professor

Eindhoven University of Technology

NETHERLANDS

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Tae Hyoung Kim

Research Interests

Contact this professor

About

Articles (29)

A Time-Based PAM-4 Transceiver Using Linear Voltage-to-Time Converter and Single Path PAM-4 Decoder with Fast-Stochastic Calibration

A 65-nm 55.8-TOPS/W Compact 2T eDRAM-Based Compute-in-Memory Macro With Linear Calibration

SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor for IoT Devices

A 2.793 μW Near-Threshold Neuronal Population Dynamics Trajectory Filter for Reliable Simultaneous Localization and Mapping

A Graph-Based Accelerator of Retinex Model With Bit-Serial Computing for Image Enhancements

Convolutional Window-Inspired Similarity-Aware Computation-in-Memory for Energy Saving

FlexDCIM: A 400 MHz 249.1 TOPS/W 64 Kb Flexible Digital Compute-in-Memory SRAM Macro for CNN Acceleration

Learn to Establish and Achieve Professionalism at Asian Solid-State Circuits 2024 Was a Success (LEAP) [Women in Circuits Corner]

Time-Based Sensing With Linear Current-to-Time Conversion for Multi-Level Resistive Memory

A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks

A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations

FlexSpin: A CMOS Ising Machine With 256 Flexible Spin Processing Elements With 8-b Coefficients for Solving Combinatorial Optimization Problems

A High-Resolution Discrete-Time Second-Order ΣΔ ADC with Improved Tolerance to KT/C Noise Using Low Oversampling Ratio

A 2.5-GHz Dynamic Performance-Enhanced Nonlinear DAC-Based Direct-Digital Frequency Synthesizer in 65-nm CMOS Process

A Reconfigurable Step-Down Switched-Capacitor Power Converter Using Optimized Partial Series-Parallel (OPSP) Topology

HGRP: A 181-μ W Real-Time Hand Gesture Recognition Processor Based on Bi-Directional Convolution and Iteration-Free Feature Clustering

A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation

A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based ΔΣ ADC Suitable for DVFS

An Inductance-Variation-Insensitive Buck Converter Using a Dynamic Ramp Compensation With Slope Sensing Technique

A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array

A 184-μW Error-Tolerant Real-Time Hand Gesture Recognition System With Hybrid Tiny Classifiers Utilizing Edge CNN

A Robust Time-Based Multi-Level Sensing Circuit for Resistive Memory

A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks

A 6-Gb/s PAM-3 Transceiver With Background Time-Varying Offset Sensing and Compensation

A Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration

A Reconfigurable CMOS Ising Machine With Three-Body Spin Interactions for Solving Boolean Satisfiability With Direct Mapping

BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory

Transposable 9T-SRAM Computation-In-Memory for on-Chip Learning With Probability-Based Single-Slope SAR Hybrid ADC for Edge Devices

A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks

Collaborators (5)

YONGTAE KIM

Yong Shim

Wen Siang Lew

Bongjin Kim

Pieter Harpe

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