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Yanan Sun

Associate Professor

Shanghai Jiao Tong University

China

Research Interests

Articles (17)

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2026

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2026

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2023

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2023

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2023

Collaborators (3)

Mingoo Seok

Columbia University

UNITED STATES

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Zhigang Ji

Professor

Shanghai Jiao Tong University

CHINA

View details

Fengbin Tu

Assistant Professor

The Hong Kong University of Science and Technology (Guangzhou)

CHINA

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Yanan Sun

Research Interests

Articles (17)

HEIRS-PS: Hybrid Three-dimensional RRAM- and SRAM-CIM for Pipelined Sparse Multi-Task Transformer Acceleration

A Heterogeneous CIM Architecture With Splittable Nonvolatile Computing-in-SRAM Cell Pairs Enabling Efficient On-Chip Neural Network Inference

DBP-CIM: Energy-Efficient 8T SRAM-Based Diagonal-Block Parallel Computing-in-Memory With Compact Data Layout for Arithmetic Operations

A Full-Digital Heterogeneous Computing-in-Memory With Dual-Bit Serialized Weight Stream and Ping-Pong Computing for Efficient Transformer Acceleration

Harmonia: Algorithm-Hardware Co-Design for Memory- and Compute-Efficient BFP-Based LLM Inference

IEEE WiCAS and YPCAS Host Joint Event IEEE at ISICAS 2025 in Qingdao to Explore Career Reshaping in the AI-Powered Era [CASS Conference Highlights]

Hop-CIM: An all-digital two-level approximate SRAM-CIM macro for high energy-efficient HNN acceleration with data-aware early exit and column-wise partial-sum reuse

HyCTor: A Hybrid CNN-Transformer Network Accelerator With Flexible Weight/Output Stationary Dataflow and Multicore Extension

Robust Monolithic 3D Carbon-Based Computing-in-SRAM With Variation-Aware Bit-Wise Data-Mapping for High-Performance and Integration Density

HEIRS: Hybrid Three-Dimension RRAM- and SRAM-CIM Architecture for Multi-task Transformer Acceleration

BASER: Bit-Wise Approximate Compressor Configurable In-SRAM-Computing for Energy-Efficient Neural Network Acceleration With Data-Aware Weight Remapping Method

Descriptor: MOSFET Electrical Simulation Dataset (MESD)

CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration

A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead

A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip

CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration

BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars

Collaborators (3)

Mingoo Seok

Zhigang Ji

Fengbin Tu

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