Yvon Savaria

Professor

Polytechnique Montréal

Canada

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About

Yvon Savaria is a Professor at Polytechnique Montréal in Canada. His research focuses on areas such as high-voltage protection circuit design, FPGA implementations for packet processing, and energy harvesting for IoT applications. He has contributed significantly to the development of modular P4 programming and advanced neural network structures for transient modeling in nonlinear circuits.

Articles (28)

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2022

Collaborators (7)

Yves Blaquière

Professeur

École de technologie supérieure

CANADA

Professeur des Université

Sorbonne Université

FRANCE

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Yvon Savaria

Research Interests

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About

Articles (28)

Enabling Rank-Based P4 Programmable Schedulers: Requirements, Implementation, and Evaluation on BMv2 Switches

P4Muse: Enabling Modular P4 Programming via Compiler-Managed Code Merging Without Syntax Modifications

Integrated High-Voltage Bidirectional Protection Switches with Overcurrent Protection: Review and Design Guide

HLSCAM: Fine-Tuned HLS-Based Content Addressable Memory Implementation for Packet Processing on FPGA

High-Efficiency Wide Input Power Range Three-Phase Radio Frequency Energy Harvester for IoT Applications

5G Fronthaul in Modular P4: eCPRI Protocol Processing and Precise BMv2 Timestamps for PTP-1588

Long Short-Term Memory Neural Network Combined With a Hybrid-Modular Clockwork Structure for Transient Modeling of Nonlinear Circuits

P4THLS: A Templated HLS Framework to Automate Efficient Mapping of P4 Data-Plane Applications to FPGAs

Network Attack Classification with a Shallow Neural Network for Internet and Internet of Things (IoT) Traffic

A Half-Bridge Gate Driver With Self-Adjusting and Tunable Dead-Time Modes for Efficient Switched-Mode Power Systems

Enhanced Dynamic Regulation in Buck Converters: Integrating Input-Voltage Feedforward With Voltage-Mode Feedback

Thermal Analysis of System in Package Considering Boundary Conditions for Long-Term Reliability Studies

PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA

Incremental reinforcement learning for multi-objective analog circuit design acceleration

Statistical Hardware Design With Multimodel Active Learning

A 32-mV Supply Ring Oscillator Composed of Modified Schmitt Trigger Delay Cells for Integrated Start-up Circuits in DC Energy Harvesting Systems

Characterization and Selection of WiFi Channel State Information Features for Human Activity Detection in a Smart Public Transportation System

Digital Compensation of Timing Skew Mismatches in Time-Interleaved ADCs by Source Separation

Accurate On-Chip Thermal Peak Detection Based on Heuristic Algorithms and Embedded Temperature Sensors

Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers

A Memristive Cell with Long Retention Time in 65 nm CMOS Technology

Symbolic Analysis for Data Plane Programs Specialization

An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform

A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices

DR-PIFO: A Dynamic Ranking Packet Scheduler Using a Push-In-First-Out Queue

Deep Independent Recurrent Neural Network Technique for Modeling Transient Behavior of Nonlinear Circuits

Enhanced Artificial Vision for Visually Impaired Using Visual Implants

Towards Real-Time Monitoring of Thermal Peaks in Systems-on-Chip (SoC)

Collaborators (7)

Yves Blaquière

Ahmed Lakhssassi

Jean Pierre David

Ahmad Hassan

Tarek Ould-Bachir

Ahmed Ragab

Bertrand Granado

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