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ETH Zurich

Doctoral or Postdoctoral Position in Low-Jitter Clock Generation for Single-Photon RGB-D Image Sensors ETH Zurich in Switzerland

Degree Level

PhD, Postdoc

Field of study

Electrical Engineering

Funding

Available

Deadline

Nov 30, 2026

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Country

Switzerland

University

ETH Zurich

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Keywords

Electrical Engineering
Robotics
Frequency Synthesis

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About this position

ETH Zurich's Energy-Efficient Circuits and Intelligent Systems Group (EECIS) is seeking a doctoral or postdoctoral researcher to develop low-jitter frequency synthesis and clock-generation circuits for a next-generation single-chip RGB-D image sensor for robotics.

The international industry-academia project combines colour imaging with direct time-of-flight depth sensing on a single-photon avalanche diode (SPAD) array. Because depth accuracy depends directly on the timing precision of large parallel time-to-digital converters, the research will address clocking errors at the picosecond scale.

The researcher will develop an ultra-low-jitter, low-power phase-locked loop and investigate energy-efficient frequency synthesis and clock distribution across the sensor array. The work spans architecture and system-level specification, analog and mixed-signal circuit design, layout, tape-out in advanced CMOS technology, chip characterization, and refinement based on measurement results. The completed circuits will support integration into the sensor system-on-chip.

EECIS works on energy-efficient circuits and systems for miniaturized computing platforms, including analog interfaces, optical and RF transceivers, frequency synthesizers, power-management units, and data converters. The researcher will collaborate closely with an industrial chip-design partner, ETH Zurich robotics researchers, and an international team, while using a complete IC design and verification environment, the ETH Microelectronics Design Center, advanced CMOS multi-project wafer processes, and specialized measurement laboratories.

The position also includes publishing results at leading venues, presenting at international conferences, and contributing to group teaching activities. The opening is supervised by Prof. Taekwang Jang.

Funding details

Available

What's required

Applicants must hold a Master's or Ph.D. degree in electrical engineering or a closely related field, with excellent grades. A solid background in analog and mixed-signal integrated-circuit design is required. Experience with PLLs, oscillators, clock generation, or data converters is advantageous, as is hands-on experience with Cadence Virtuoso or similar tools. Previous tape-out or laboratory measurement experience is a plus. Candidates should have strong analytical skills, enthusiasm for high-performance circuit design, the ability to work independently and in an international academia-industry team, and excellent written and spoken English. The application must include a maximum one-page motivation letter, curriculum vitae with publication list if applicable, Bachelor's and Master's degree certificates and transcripts, and contact information for two references.

How to apply

Submit the application exclusively through the online application portal. Include a one-page motivation letter, CV, degree certificates and transcripts, and contact details for two references. Direct questions to Prof. Dr. Taekwang Jang by email; applications are not accepted by email or post.

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