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The University of Manchester
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PhD in Smart Network-on-Chip Design for Congestion Management in 2.5D Chiplet Systems The University of Manchester in United Kingdom
Degree Level
PhD
Field of study
Electrical Engineering
Funding
Available
Deadline
Nov 15, 2026
Country
United Kingdom
University
The University of Manchester
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About this position
PhD opportunity at The University of Manchester in Smart Network-on-Chip Design for Congestion Management in 2.5D Chiplet Systems.
This 3.5-year fully funded PhD sits within the Computer Science research theme and addresses a timely challenge in semiconductor system design: how to build intelligent communication fabrics for heterogeneous chiplet-based systems. Modern chiplet and multi-chip module architectures bring together CPUs, GPUs, AI accelerators, and memory stacks on a common interposer, improving flexibility and performance while creating new pressure on the interconnect fabric. The project aims to design a Smart Network-on-Chip (SNoC) that integrates intelligence into asynchronous communication hardware to manage congestion adaptively and maintain high-performance data movement across dynamic workloads.
Research directions may include lightweight inference engines, learning-based routing policies, integration of adaptive intelligence into router microarchitectures, and distributed traffic management strategies. The work is grounded in an existing RTL-verified asynchronous NoC IP, providing a strong hardware base for further innovation. The project is also open to ideas involving LLM-aided design methodologies and agentic approaches for automating and improving intelligent NoC architecture design.
The advert states that two motivated PhD candidates are sought. Suitable applicants should have, or expect to achieve, at least a 2.1 honours degree or a master’s (or international equivalent) in a relevant science or engineering discipline. A background in digital design, computer architecture, and/or the backend digital design flow is desirable, and prior experience with RTL design, system architecture simulation, or machine learning for hardware would be advantageous. This position is restricted to UK nationals only.
The studentship is fully funded for 3.5 years. The successful candidate will receive an annual tax-free stipend of £21,805 (UKRI rate for 2026/27), expected to rise annually, and tuition fees will be paid. The start date is January 2027. The advert recommends applying early, as it may be removed before the deadline.
To apply, contact the main supervisor Dr. Davide Bertozzi and include details of your current level of study, academic background, relevant experience, and a paragraph describing your motivation for pursuing the project. The application deadline is 15 November 2026.
Funding details
Available
What's required
Applicants should have, or expect to achieve, at least a 2.1 honours degree or a master’s (or international equivalent) in a relevant science or engineering discipline. A background in digital design, computer architecture, and/or the backend digital design flow is preferred. Prior experience with RTL design, system architecture simulation, and/or machine learning for hardware is a plus. This position is for UK nationals only.
How to apply
Contact the main supervisor, Dr. Davide Bertozzi, to apply. Include your current level of study, academic background, relevant experience, and a paragraph explaining your motivation for the PhD project.
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Prepare your application
Review drafts and confirm requirements with the university.
Make your next move.
Prepare your application
Review drafts and confirm requirements with the university.