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ETH Zurich

Just Landed

Doctoral or Postdoctoral Position in Energy-Efficient High-Speed SAR ADCs for Next-Generation Wireline Transceivers ETH Zurich in Switzerland

Degree Level

PhD, Postdoc

Field of study

Electrical Engineering

Funding

Available

Deadline

Nov 30, 2026

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Country

Switzerland

University

ETH Zurich

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Keywords

Electrical Engineering

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About this position

ETH Zurich’s Energy-Efficient Circuits and Intelligent Systems Group (EECIS) is seeking a doctoral or postdoctoral researcher to develop energy- and area-efficient high-speed analog-to-digital converters for next-generation wireline transceivers serving AI data centers.

The project addresses the interconnect bottleneck created by large-scale GPU clusters. It aims to develop active electrical cables with extended reach using space-time coded signaling, reduced baud rates, and ADC-based receivers with digital equalization. The researcher will focus on the unit ADC, a key building block of a time-interleaved array and a major contributor to receiver power and area.

The research will investigate multi-GS/s successive-approximation-register (SAR) ADCs with a minimal silicon footprint. Topics include aggressive capacitive DAC scaling, loop-unrolled and time-based architectures, background calibration, time-interleaving, low-jitter clock distribution, and integration of the receiver front end with the ADC sampler.

Activities span behavioral modeling and specification derivation from link requirements through circuit design, layout, tape-out in advanced CMOS technology, chip characterization, measurement-driven refinement, and integration into the complete transceiver. The researcher will publish results at leading venues, present at international conferences, and contribute to group teaching.

EECIS provides an IC design and verification environment, tape-out support through the ETH Microelectronics Design Center, access to advanced CMOS processes via multi-project wafer runs, and an in-house measurement laboratory. The position includes close collaboration with an industrial partner and participation in a diverse international research team working on energy-efficient circuits and systems for future computing platforms.

Funding details

Available

What's required

Applicants must hold a Master's or Ph.D. degree in electrical engineering or a closely related field, with excellent grades. A solid background in analog and mixed-signal integrated circuit design is required. Experience with data converters, especially SAR or time-interleaved ADCs, is advantageous. Hands-on experience with Cadence Virtuoso or similar tools is expected; previous tape-out or laboratory measurement experience is beneficial. Applicants should have strong analytical skills, enthusiasm for high-performance circuit design, the ability to work independently and in an international academia–industry team, and excellent written and spoken English.

How to apply

Submit the application exclusively through the online application portal. Include a one-page motivation letter, CV with publications if applicable, Bachelor's and Master's certificates and transcripts, and the names and contact information of two references. Direct questions to Prof. Dr. Taekwang Jang by email; applications sent by email or post will not be considered.

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