Azad Naeemi

Professor

Georgia Institute of Technology

United States

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Azad Naeemi is a Professor at the Georgia Institute of Technology in the United States. His research focuses on advanced semiconductor technologies, including memory circuit design, phase-field modeling of ferroelectrics, and the evaluation of plasmonic devices. Recent articles authored by him encompass topics such as content addressable memories, GAAFET technology, and unconventional computing with nanotechnology.

Articles (28)

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2020

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2020

Collaborators (10)

Chenyun Pan

The University of Texas at Arlington

UNITED STATES

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Amit Ranjan Trivedi

University of Chicago

UNITED STATES

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Aida Todri-Sanial

Full Professor

Eindhoven University of Technology

NETHERLANDS

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Tony Low

University of Minnesota

UNITED STATES

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Giovanni Finocchio

Assistant Professor

Università degli Studi di Palermo

ITALY

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Patrick Reynaert

Full Professor

KU Leuven

BELGIUM

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Xiaobo Hu

Professor

University of Notre Dame

UNITED STATES

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Dayane Reis

Assistant Professor

University of South Florida

UNITED STATES

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Andrii Chumak

Universität Wien

AUSTRIA

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Joseph S. Friedman

UNITED STATES

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Azad Naeemi

Research Interests

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About

Articles (28)

Cross-Layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search

GT3: An Open-Source 3-nm GAAFET PDK and Platform for End-to-End Evaluation of Emerging Technologies

Investigating the Switching Dynamics of Antiferroelectric Capacitor Using Multidomain Phase-Field Approach

Roadmap for unconventional computing with nanotechnology

Compact Physical Model for Ferroelectric/Antiferroelectric/Dielectric Mixed Phase Capacitors

Comparison of Photonic to Plasmonic Mode Converters for Plasmonic Multiple-Input Devices

Design Considerations for Sub-1-V 1T1C FeRAM Memory Circuits

Evaluation of a Plasmon-Based Optical Integrated Circuit for Error-Tolerant Streaming Applications

Impact of Technology Scaling and Back-End-of-The-Line Technology Solutions on Magnetic Random-Access Memories

Design of a Compact Spin-Orbit-Torque-Based Ternary Content Addressable Memory

A Compact Model for Ferroelectric Capacitors Based on Multidomain Phase-Field Framework

A Comprehensive Modeling Platform for Interconnect Technologies

A Drift-Diffusion Based Modeling and Optimization Framework for Nanoscale Spin-Orbit Torque Devices

Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis

Benchmarking of spin-orbit torque vs spin-transfer torque devices

Bipolar Electric-Field Switching of Perpendicular Magnetic Tunnel Junctions through Voltage-Controlled Exchange Coupling

Evaluating the Performances of the Ultralow Power Magnetoelectric Random Access Memory with a Physics-Based Compact Model of the Antiferromagnet/Ferromagnet Bilayer

High-Density Spin-Orbit Torque Magnetic Random Access Memory with Voltage-Controlled Magnetic Anisotropy/Spin-Transfer Torque Assist

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits - Vol. 8, No. 1

A Theoretical Study of Multidomain Ferroelectric Switching Dynamics with a Physics-Based SPICE Circuit Model for Phase-Field Simulations

Accurate determination of interlayer resistivity of 2-D layered systems: Graphene case study

Benchmarking and Optimization of Spintronic Memory Arrays

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits - Volume 6, No. 2

Materials Requirements of High-Speed and Low-Power Spin-Orbit-Torque Magnetic Random-Access Memory

Modeling and Optimization of Plasmonic Detectors for Beyond-CMOS Plasmonic Majority Logic Gates

Simulation of the Magnetization Dynamics of a Single-Domain BiFeO Nanoisland

Understanding the Switching Mechanisms of the Antiferromagnet/Ferromagnet Heterojunction

Valley-Spin Logic Gates

Collaborators (10)

Chenyun Pan

Amit Ranjan Trivedi

Aida Todri-Sanial

Tony Low

Giovanni Finocchio

Patrick Reynaert

Xiaobo Hu

Dayane Reis

Andrii Chumak

Joseph S. Friedman

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