Xiaobo Hu

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University of Notre Dame

United States

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About

Dr. Xiaobo Hu is a Professor at the University of Notre Dame in the United States. His research interests encompass advanced computing technologies, including 5G networks, in-memory computing, and neural network accelerators. Dr. Hu has authored several significant papers, focusing on topics such as scheduling frameworks for radio access networks, design automation for memory technologies, and robust training methods for deep learning accelerators.

Recent Grants

Grant: Close

E2CDA: Type I: EXtremely Energy Efficient Collective ELectronics (EXCEL)

Open Date: 2016-09-01

Close Date: 2019-08-31

Grant: Close

II-New: Infrastructure for Supporting Biomedical Application Algorithms, Runtime Development and Resource Management

Open Date: 2016-08-01

Close Date: 2019-07-31

Grant: Close

EAGER: An Analog Hardware System for Solving Boolean Satisfiability

Open Date: 2016-07-15

Close Date: 2018-06-30

Grant: Close

IRES: U.S.-Hungary Research Experience for Students on Non-Boolean Computer Architectures

Open Date: 2014-09-01

Close Date: 2018-08-31

Grant: Close

CSR: Small: Collaborative Research: Reliability Driven Resource Management of Multi-Core Real-Time Embedded Systems

Open Date: 2013-10-01

Close Date: 2017-09-30

Articles (23)

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2022

Collaborators (16)

Hai Li

Clare Boothe Luce Professor

Duke University

UNITED STATES

Xiaobo Hu

Research Interests

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About

Recent Grants

Articles (23)

Shared-PIM: Enabling Concurrent Computation and Data Flow for Faster Processing-in-DRAM

5G-TPS: A Two-Phase Real-Time Scheduling and Adaptation Framework for 5G Radio Access Networks

Cross-Layer Design and Design Automation for In-Memory Computing based on Non-Volatile Memory Technologies

EvaCAM: A Circuit-level Evaluation Tool for General Content Addressable Memories

NeFT: Negative Feedback Training to Improve Robustness of Compute-In-Memory DNN Accelerators

A Physics-Based Model for Oxide–Semiconductor-Based Ferroelectric Field-Effect Transistors

Neuro-Symbolic Computing: Advancements and Challenges in Hardware–Software Co-Design

Accelerating Finite-Field and Torus Fully Homomorphic Encryption via Compute-Enabled (S)RAM

A Computing-in-Memory-Based One-Class Hyperdimensional Computing Model for Outlier Detection

Compute-in-Memory-Based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections

Report on the 2023 Embedded Systems Week (ESWEEK)

U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators

Accelerating Recommendation Systems With In-Memory Embedding Operations

MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures

A Reconfigurable FeFET Content Addressable Memory for Multi-State Hamming Distance

Design of a Compact Spin-Orbit-Torque-Based Ternary Content Addressable Memory

An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs

Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities

Report on the 2022 Embedded Systems Week (ESWEEK)

ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference

Sky-TCAM: Low-Power Skyrmion-Based Ternary Content Addressable Memory

Deadline and Reliability Aware Multiserver Configuration Optimization for Maximizing Profit

Cross-Coupled Gated Tunneling Diodes With Unprecedented PVCRs Enabling Compact SRAM Design—Part I: Device Concept

Collaborators (16)

Hai Li

Wolfgang Porod

Yifan Qin

Jason Cong

Dailin Gan

Aviral Shrivastava

Ramin Rajaei

Yu Cao

Dayane Reis

Hussam Amrouch

Peng Li

Miroslav Pajic

Gert Cauwenberghs

Sri Parameswaran

Azad Naeemi

Song Han

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