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Hayoung Lee

Assistant Professor

Ajou University

South Korea

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About

Hayoung Lee is an Assistant Professor at Ajou University, South Korea. His research areas focus on advanced diagnostic methods, built-in self-repair systems, and efficient test architectures for memory technologies and AI accelerators. Recent publications include works on multistage diagnosis, cost-effective testing solutions, and redundancy analysis using GPU technology.

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Collaborators (2)

Seung Ho Shin

Yonsei University

SOUTH KOREA

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Sungho Kang

Professor

Yonsei University

SOUTH KOREA

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Hayoung Lee

Research Interests

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About

Articles (23)

An Error Correction Code-Based Self-Test for Buffer-Die in High-Bandwidth Memory

DPR-PIM: Diagnosis and Pipelined Repair Architecture for Processing-in-Memory

STARFISH: Scalable TSV Architecture for Repairing Faults in Stacked HBM

Subarray-Based Victim-Centric Per-Row Counting for Mitigating RowHammer

Multistage Enhanced Diagnosis With Fault Candidate Reduction

A Built-In Self-Repair With Maximum Fault Collection and Fast Analysis Method for HBM

An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory

A Robust Test Architecture for Low-Power AI Accelerators

A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing

Effective Parallel Redundancy Analysis Using GPU for Memory Repair

VASE: Vector Memory Using Bit-Level Address Segmentation for High-Speed Memory Testing

GRAP: Efficient GPU-Based Redundancy Analysis Using Parallel Evaluation for Cross Faults

RA-Aware Fail Data Collection Architecture for Cost Reduction

A New Fail Address Memory Architecture for Cost-Effective ATE

A New ISA for High-Speed and Area-Efficient ALPG

A New Pipelined Output Data Reducer of BOST for Improved Parallelism

An Area-Efficient Systolic Array Redundancy Architecture for Reliable AI Accelerator

A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing

Effective Parallel Redundancy Analysis Using GPU for Memory Repair

TRUST: Through-Silicon via Repair Using Switch Matrix Topology

STRAIT: Self-Test and Self-Recovery for AI Accelerator

Multibank Optimized Redundancy Analysis Using Efficient Fault Collection

ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM

Collaborators (2)

Seung Ho Shin

Sungho Kang

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