Jun-Eun Park

Sungkyunkwan University

South Korea

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Articles (21)

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2025

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2022

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2022

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2022

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2020

Collaborators (4)

Mingoo Seok

Columbia University

UNITED STATES

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Deog-Kyoon Jeong

Professor

Seoul National University

SOUTH KOREA

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Young-Ha Hwang

Assistant Professor

Soongsil University

SOUTH KOREA

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Kwanseo Park

Yonsei University

SOUTH KOREA

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Jun-Eun Park

Research Interests

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Articles (21)

A Compact Power-on-Reset Circuit With Configurable Brown-Out Detection

A 500 mA Output-Capacitorless NMOS LDO With Dynamic Load Range Adaptation Achieving Fast Settling Time and Enhanced PSR for Chiplet Power Managements

A Fast-Transient One-Shot Droop Recovery Digital LDO With Reinforcement-Learning Droop Compensation for D2D Interfaces

A Fully Integrated Switched-Capacitor Voltage Regulator With Switching-Aware Ripple Injection LDO Achieving up to 77% Ripple Reduction

A 92.7% Peak Efficiency Self-Starting Boost Converter With MPPT and Phase Frequency Detector Based Multi Current Detector for Energy Harvesting Systems With a Minimum Input Source Impedance of 1 Ω

Design of a High-Gain Multi-Input LNA with 16.4 Degree Phase Shift Within the 32 dB Gain Range

100-nW Wake Up Receiver With -42.3 dBm Sensitivity for Real-Time Location Systems

A 0.6-to-1.1-V 2-A Dead-Zone-Based Dual-Loop Ring-Amplifier LDO for High-Current-Density Custom HBM Applications

A Design of a 100-MHz Fully Integrated Digital Pulse Width Modulation Three-Level Buck Converter Using Package Bond-Wire Inductor

A Low Power Memory-Integrated Hardware BNN-MLP Model on an FPGA for Current Signals in a Biosensor

A Capacitorless External-Clock-Free Fully Synthesizable Digital LDO With Time-Based Load-State Decision and Asynchronous Recovery

A Design of Analog PLL-Based Self-Calibrated Open-Loop FSK Modulator for BLE Advertising Transmitter

A Surface Acoustic Wave-Based PM 1.0 Fine Dust Detection System Using Full Digital Time-Interleaved Counters

Analysis of Power-Supply-Rejection Enhancement Techniques for Low-Dropout Regulators

An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications

An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector

An N-Type Pseudo-Static eDRAM Macro with Reduced Access Time for High-Speed Processing-in-Memory in Intelligent Sensor Hub Applications

A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques

A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme

Collaborators (4)

Mingoo Seok

Deog-Kyoon Jeong

Young-Ha Hwang

Kwanseo Park

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