Kwanseo Park

Yonsei University

South Korea

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Articles (24)

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2021

Collaborators (6)

Deog-Kyoon Jeong

Professor

Seoul National University

SOUTH KOREA

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Young-Ha Hwang

Assistant Professor

Soongsil University

SOUTH KOREA

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Borivoje Nikolic

University of California, Berkeley

UNITED STATES

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Jun-Eun Park

Sungkyunkwan University

SOUTH KOREA

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Min-Seong Choo

Assistant Professor

Hanyang University - Ansan Campus

SOUTH KOREA

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Kyoungtae Lee

University of California, Berkeley

UNITED STATES

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Kwanseo Park

Research Interests

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Articles (24)

A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces

A Compact Power-on-Reset Circuit With Configurable Brown-Out Detection

A 1.19-pJ/b 32-Gb/s Baud-Rate Receiver Employing 2UI Integrated Pattern-Based CDR and DFE Adaptation Without Data-Level Reference

A 14-to-32-Gb/s Deadzone-Free Referenceless CDR With Autocovariance-Based Seamless Frequency Detector in 40-nm CMOS Technology

A 16-to-30-Gb/s 1.03-pJ/b Baud-Rate Receiver With Referenceless CDR Employing Integrated Pattern Decoding Technique in 28-nm CMOS

A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver

An 18-Tb/s/mm PAM-3 On-Chip Link With Jitter-Suppressing 3T4T Coding and FFE-Based Crosstalk Cancellation for Memory Interfaces

SSCS Seoul Chapter Members Gather at ISSCC 2025 [Chapters]

Analysis of Stochastic Phase-Frequency Detector in 2x Oversampling Clock and Data Recovery

Analysis of Stochastic Phase-Frequency Detector in 2x Oversampling Clock and Data Recovery

A 0.09-pJ/b/dB 28-Gb/s Digital CDR With ISI-Resistant Phase Detector

A 3×12-Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS

A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS

A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS

A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation

A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link

Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector

Design Techniques for a 6.4–32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency–Phase Detector

An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration

A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS

An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS

A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS

Collaborators (6)

Deog-Kyoon Jeong

Young-Ha Hwang

Borivoje Nikolic

Jun-Eun Park

Min-Seong Choo

Kyoungtae Lee

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