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Tsung-Yi Ho

Professor

The Chinese University of Hong Kong (CUHK)

Hong Kong

Research Interests

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Articles (20)

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2026

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2025

Collaborators (10)

Ting-Chi Wang

Professor

National Tsing Hua University

TAIWAN

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Takashi Sato

教授 / Professor

Kyoto University

JAPAN

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Ulf Schlichtmann

Professor of Electronic Design Automation

Technical University of Munich

GERMANY

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Xing Huang

Northwestern Polytechnical University

CHINA

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Bing Li

Professor

TU Ilmenau

GERMANY

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Lukas Burgholzer

Senior Researcher

Technical University of Munich

GERMANY

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Rolf Drechsler

University of Bremen

GERMANY

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Seokhyeong Kang

Assistant Professor

Pohang University of Science and Technology

SOUTH KOREA

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Robert Wille

Full and Distinguished Professor

Technical University of Munich

GERMANY

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Tsung-Wei Huang

Assistant Professor

University of Utah

UNITED STATES

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Tsung-Yi Ho

Research Interests

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Articles (20)

ConfiBench: Automatic Testbench Generation with Confidence-Based Scenario Mask and Testbench Ensemble using LLMs for HDL Design

ASP-DAC 2026: Strengthening Asia’s Expanding Role in Design Automation Research

Adaptive Control-Logic Routing with Length Matching and Fault Tolerance for FPVA Biochips Using Deep Reinforcement Learning

FlatDD: Parallel Quantum Circuit Simulation using Decision Diagram and Flat Array

Parallel Delay-Driven Layer Assignment Leveraging Hierarchical Task Graph Modeling for Advanced Technology Nodes

FuILT-S: Full Chip ILT With Unified Boundary Healing and SRAF Co-Optimization

Efficient Multiarray Parallel Scheduling for In-Memory Computing

PAPlace: Performance-Driven Differentiable Analog Placement

CHOP: Clustered Hybrid Optimization for Logic Synthesis With Self-Supervised Prediction

Defining and Evaluating Physical Safety for Large Language Models

AgeBalance: Low-Cost Lifetime Extension for SRAM-Based PIM Accelerators

Ckt2Vec: Efficient Electrical Encoding for Analog Circuit Representations in Vector Space

RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization

THLR: A Top-down Hierarchical Logic Rewrite Framework for Xor-Majority-Inverter Graphs

ICCAD 2025: First Time Outside the United States and a Record-Breaking Edition

Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System

Selecting Nets to Rip Up and Reroute via SAT

Gradient-Guided RC Weighting for Timing-Driven Global Routing

IDDA-3D: Inter-Die Delay Aware Timing-Driven Placement on Face-to-Face Bonded 3D ICs

G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner using Task Graph Parallelism

Collaborators (10)

Ting-Chi Wang

Takashi Sato

Ulf Schlichtmann

Xing Huang

Bing Li

Lukas Burgholzer

Rolf Drechsler

Seokhyeong Kang

Robert Wille

Tsung-Wei Huang

Make your next move.