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ETH Zurich
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Doctoral or Postdoctoral Position in Full-Duplex Wireline Transceivers and Echo Cancellation ETH Zurich in Switzerland
Degree Level
PhD, Postdoc
Field of study
Signal Processing
Funding
Available
Deadline
Nov 30, 2026
Country
Switzerland
University
ETH Zurich
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About this position
ETH Zurich's Energy-Efficient Circuits and Intelligent Systems Group (EECIS) is seeking a doctoral or postdoctoral researcher to develop full-duplex wireline transceivers for next-generation AI data centers.
The Innosuisse innovation project addresses the growing connectivity bottleneck between thousands of GPUs. The research aims to extend the reach of high-speed electrical cables through space-time coded signaling, lower-baud-rate transmission, ADC-based reception, and digital equalization. The position focuses on simultaneous bidirectional signaling, in which data is transmitted and received over the same wire at the same time.
The central technical challenge is echo cancellation: the receiver must recover a weak far-end signal while suppressing a much stronger echo from its own transmitter. The researcher will integrate SBD into a space-time coded transceiver, developing an analog hybrid in the transmitter, a high-speed subtraction node in the receiver, and combined analog-digital echo-cancellation techniques.
Research activities include system modelling, circuit specification, analog and mixed-signal CMOS design, layout, tape-out, chip characterization, and refinement based on measurement results. The work combines high-precision analog circuits with digital signal processing and involves close collaboration with an industrial partner. The researcher will also publish results, present at international conferences, and contribute to group teaching.
EECIS provides an IC design and verification environment, tape-out support through the ETH Microelectronics Design Center, access to advanced CMOS processes, and an equipped measurement laboratory. The group works on energy-efficient circuits and systems for next-generation computing platforms, including analog interfaces, optical and RF transceivers, frequency synthesizers, power management, and data converters, within a diverse international research environment.
Funding details
Available
What's required
Applicants must hold a Master's or Ph.D. degree in electrical engineering or a closely related field with excellent grades. A solid background in analog and mixed-signal integrated circuit design is required. Knowledge of communication theory and signal processing, experience with system modelling in Python or MATLAB, and the ability to work independently in an international academic-industry team are expected. Excellent written and spoken English is required. Experience with high-speed wireline transceivers, equalization, echo cancellation, Cadence Virtuoso or similar tools is advantageous; previous tape-out or laboratory measurement experience is a plus. The application must include a motivation letter of no more than one page, a curriculum vitae with publications if applicable, Bachelor's and Master's degree certificates and transcripts, and the names and contact information of two references.
How to apply
Submit the application exclusively through the online application portal. Include a maximum one-page motivation letter, CV, degree certificates and transcripts, and contact details for two references. Direct questions to Prof. Dr. Taekwang Jang by email; applications sent by email or post will not be considered.
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